Cobalt silicide (CoSi2) has been widely utilized in MOS devices for electrical contacts and interconnect material. CoSi2 reduces device parasitic electrical resistance, and therefore enhances drive-current and performance of the devices. As device scaling extends into the deep sub-micron regime, shallow source/drain junctions are important to prevent junction “punch-through” and reduce the effect of drain-induced barrier lowering (DIBL).
One method for fabricating a CoSi2 layer involves using polycrystalline CoSi2 film through conventional solid phase epitaxial growth. One problem associated with this technique is that the resultant non-uniform silicide-silicon interface could cause abnormal junction leakage current, especially in deep sub-micron devices equipped with shallow junctions. Specifically, the non-uniform interface between polycrystalline CoSi2 and Si creates localized weak-spots. The localized weak spots can form the origin of junction leakage. Current leakage can be especially severe if the depth of the junction is shallow, e.g., as in deep sub-micron devices.
Oxide-mediated epitaxial growth and related techniques have been proposed to enhance the formation of epitaxial CoSi2. These techniques make use of an oxide or titanium mediated layer to enhance the growth of epitaxial CoSi2. In these processes, excessive loss of CoSi2 during contact etching processes could result in high contact resistance and degrade the device performance and reliability.
Once a CoSi2 layer has been formed, a common, known practice to form borderless and self-aligned contacts is to form an additional layer of low-temperature PECVD silicon nitride, which functions as the etch-stop layer during contact etching. This layer preserves the junction and contact integrity by inhibiting both shallow-trench-isolation (STI) oxide gouging and excessive loss of silicide during contact-etching. A drawback associated with any additional layer, though, is the addition of a step in the device manufacturing process, which increases manufacturing costs. There is also a likelihood of device damage as a result of PID (plasma induced damage) damage during the PECVD deposition process. Also, the presence of the additional layer of silicon nitride reduces the spacing between the adjacent polysilicon electrodes, and therefore poses difficulty for subsequent inter-layer-dielectric (ILD) formation.